1. Field of the Invention
This invention relates to a data storing device, more specifically to a data storing device capable of storing a large quantity of data.
2. Description of the Related Art
A ferroelectric memory 10 using a ferroelectric capacitor is known as a data storing device. A part of the circuit structure of the conventional ferroelectric memory is depicted in FIG. 9.
In the conventional ferroelectric memory, a plurality of memory cells MC0, MC1, MC2, . . . and a sensing amplifier SA are connected to a pair of the bit lines BL and BLB. A dummy cell DC0 and another dummy cell DC1 are respectively connected to the bit line BLB and the bit line BL.
The memory cell MC0 is a memory element so called one transistor and one capacitor type memory element. That is, the memory cell MC0 includes a ferroelectric capacitor 2, and one end of the ferroelectric capacitor 2 is connected to a bit line BL through a transistor 4. The memory cell MC0 stores data corresponding to a polarization state of the ferroelectric capacitor 2.
FIG. 10A is a graph showing a relationship between a polarization state of the ferroelectric capacitor 2 and the data stored in the memory cell MC0 For example, it is defined that a value of the stored data is in "1" when the polarization state of the ferroelectric capacitor 2 is in P1, and a value of the stored data is in "0" when the polarization state of the ferroelectric capacitor 2 is in P2 in this description.
Other memory cells MC1, MC2, . . . have the same structure as the memory cell MC0.
The dummy cell DC0 includes a ferroelectric capacitor 6, and one end of the ferroelectric capacitor 6 is connected to the bit line BLB through a transistor 8. The ferroelectric capacitor 6 is designed so as to have a larger area than that of the ferroelectric capacitor 2 of the memory cell (see FIG. 10A, FIG. 10B).
The dummy cell DC1 has the same structure as the dummy cell DC0.
Although, the FIG. 9 does not completely depicts its structure, the ferroelectric memory 10 has a plurality of elements 12 (hereinafter referred to as column element) 12 which has the structure described earlier in the direction of "X".
For example, in order to read out the data stored in the memory cell MC0, it is necessary to apply a voltage representing "HIGH" state to a line EQ, and then precharging the bit line BLB and the bit line BL with the ground voltage G.
Thereafter, the memory cell MC0 is selected by applying a voltage representing a "HIGH" state to the word line WL0, while selecting the dummy cell DC0 by applying a voltage representing the "HIGH" state to a word line DWL0 for dummy cells (hereinafter referred to as dummy word line). The sensing amplifier SA detects a voltage appearing on the bit lines BL and BLB by applying a readout voltage having a predetermined value to a plate line PL and a plate line DPL for dummy cells (hereinafter referred to as dummy plate line) under the condition described above.
An electric charge .DELTA.Q1 is discharged from the ferroelectric capacitor 2 when the data "1" is stored in the memory cell MC0, and another electric charge .DELTA.Q0 is discharged from the ferroelectric capacitor 2 when the data "0" is stored in the memory cell MC0 as shown in FIG. 10A. In this way, a voltage corresponding to the electric charge discharged from the ferroelectric capacitor 2 appears on the bit line BL.
On the other hand, an electric charge .DELTA.Qs is discharged from the ferroelectric capacitor 6 of the dummy cell DC0 as shown in FIG. 10B. Thus, a voltage corresponding to the electric charge .DELTA.Qs discharged from the ferroelectric capacitor 6 appears on the bit line BLB. The value of the electric charge .DELTA.Qs is set so as to be greater than that of the electric charge .DELTA.Q0 as well as to be less than that of the electric charge .DELTA.Q1.
The sensing amplifier SA determines whether the data stored in the memory cell MC0 is either in "1" or "0" by comparing whether or not the voltage appearing on the bit line BL is greater than the voltage (the reference voltage) appearing on the bit line BLB. The data stored in the memory cell MC0 can be read out by carrying out such detection.
However, the prior art ferroelectric memory described earlier has the following problems to be resolved. In order to increase the storing capacity of the ferroelectric memory 10, it is necessary to dispose other column elements 12 in the direction "X" shown in FIG. 9, while increasing the number of memory cells included in a column element 12 in the direction of "Y".
The length of the bit lines BL and BLB becomes longer than they should be when too many memory cells such as the memory cells MC0, MC1, MC2, . . . are included in the column element 12. Under the circumstances, the value of a signal voltage which appears on the bit lines BL and BLB may be decreased and/or operating speed of the ferroelectric memory could be decreased in the readout operation.
In order to resolve the problems, a ferroelectric memory (not shown) having a structure so as to dispose another ferroelectric memory 10 symmetrically with respect to an axis a shown in FIG. 9 is proposed. By employing the structure, the number of the memory cells in the direction of "Y" can be doubled without increasing the number of memory cells MC0, MC1, MC2, . . . connected to the one column element 12. In other words, the number of memory cells in the direction of "Y" can be doubled without decreasing the value of the signal voltage and/or operating speed of the ferroelectric memory.
However, the size of the data storing device may undesirably be increased substantially proportional to the number of the memory cells when just another ferroelectric memory 10 is disposed symmetrically to the prior art ferroelectric memory 10 with respect to an axis .alpha..